DFM Parametric Yield Models for Memory IPs
DFM companies only deal with 'cells' or 'gates', but not memory IPs.
With patented technologies, Legend’s CharFlo-Memory! can enable the
parametric yield models of memory IPs.
Nowadays, most DFM companies working on parametric yield models deal with only 'cells' or 'gates', but not memory IPs. However, memory IPs have usually taken the majority of chip areas in SoC designs. Therefore, the effects of memory IPs must be addressed.
With patented technologies, Legend’s CharFlo-Memory! shall enable the parametric yield models of memory IPs. For any memory instance from either commercial or in-house memory compilers, CharFlo-Memory! can automatically generate
In memory designs, the most critical 'electric' parameter would be the 'sense-amplifier input voltage', which shall directly impact the yields if less than the noise margin. When it is combined with process variations and statistical modeling, we could get an associated probability distribution related to the parametric yield model. For any memory instance from either commercial or in-house memory compilers, CharFlo-Memory! can accurately characterize the 'sense-amplifier input voltage' at any PVT (process, voltage and temperature) through automatically recognizing those ‘critical-yield’ signals such as sense-amplifier inputs and sensing controls.
"In the DFM flow of variation-aware IC designs, both cell library and memory IPs should be characterized for parametric yield models across process variations." said Dr. You-Pang Wei, president and chief executive officer of Legend Design Technology, Inc. "For cell library, there have already had the EDA tools for statistical timing and extraction results. For memory IPs, Legend’s CharFlo-memory! can be applied for extracting parametric yield models by ‘critical-path’ circuit simulation and ‘critical-yield’ signal analysis. We are fully committed to provide robust DFM solutions that enable the parametric yield models associated with memory IPs in SoC designs."
Legend Design Technology Inc. is a leading provider of circuit simulation and semiconductor IP characterization software for SoC designs. With an emphasis on productivity and value, Legend’s CharFlo-Memory! toolset revolutionizes the time-consuming and error-prone processes associated with characterization. MSIM is Legend’s high-accuracy SPICE circuit simulator with great convergence and extensive model support. Turbo-MSIM is Legend’s high-speed and high-capacity circuit simulator ideal for timing and power simulation, and function verification. Both simulators are well designed for nanometer technology challenges, and provide excellent price performance. For more information, visit www.LegendDesign.com.