Vendors team on manufacturability
 A
design-for-manufacturing standard-cell library solution specifically
targeted at improving yield has been created by Prolific Inc., Circuit
Semantics Inc. and Legend Design Technology Inc.
As designs move to
ever-finer process geometries below 130 nanometers, several physical
effects have a negative impact on yield and reliability. To deal with
those effects, said the companies, engineers will have to apply
design-for-manufacturing (DFM) techniques.
The companies assert that
the logical place to start is with standard-cell libraries. Standard
cells are critical in achieving a manufacturable design, blending logic
design information (netlists) with design trade-offs of performance,
power, area and yield (cell architecture) and manufacturing process
requirements (design rules). Moreover, standard cells are used
repeatedly throughout a design.
Those factors make them the logical focus of a move toward manufacturability, said the companies.
But applying DFM
techniques like guardbanding without guidance can often increase the
overall chip area. To deal with that problem, Prolific has developed
new DFM standard-cell libraries.
Prolific claims that 70
to 80 percent of DFM practices can be implemented without an area
penalty. And it is within those parameters that Prolific has built the
new DFM library solution.
Manufacturing enhanced
Prolific says its silicon intellectual property (IP) addresses more
than 20 manufacturing-enhancement practices. These include decreasing
the likelihood of contact and via failures by increasing contact/via
metal overlap; using wider and longer metal end-of-line extensions; and
using redundant vias and contacts. The number of critical features can
be reduced by limiting poly and diffusion routing, using straight
transistors, minimizing the number of vertices and avoiding forbidden
pitches, the company said.
Optical proximity
correction and other resolution enhancement technologies (RETs) are
also critical aspects of improving manufacturability, said Prolific.
Integrating RET-friendly design styles will not only reduce RET
layout-processing complexity and mask-making cycle time and cost, it
will also ensure best silicon performance. DFM RET recommendations
include using rectangular line ends, forbidding circular or oval
shapes, and avoiding short-cropped corners, small zigzags and jogs, and
certain pitches.
The Prolific DFM silicon
IP is integrated with the company's ProGenesis layout generation tool,
the DynaCell characterization tool from Circuit Semantics and the MSIM
circuit simulator from Legend Design Technology.
The combination, said the companies, allows users to home in on creating DFM-savvy designs that don't suffer area penalties.
Pricing for the Prolific
DFM IP starts at $25,000 for 100 cells. The IP is pre-optimized for
130-nm and 90-nm process technologies, customer design requirements
(performance, power, area) and yield.
Michael Santarini is senior editor covering electronic design automation for EE Times.
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