Legend tool automates memory characterization

By Stephan Ohr
EE Times
(05/22/01, 3:04 p.m. EST)

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SUNNYVALE, Calif. — Legend Design Technology Inc. will introduce an automatic memory characterization tool at next month's Design Automation Conference (DAC). The MemChar product offers a largely transparent method for characterizing memory blocks, according to You-Pang Wei, Legend's director of engineering.

System-on-chip (SoC) designers typically need to integrate memories, logic and control functions, Wei said. To use those embedded memories in IC designs, an accurate timing and power model is a must for simulation, verification and synthesis, for example. To generate timing and power models, characterization requires numerous circuit simulations with the appropriate Spice models.

Legend's tools extract parasitic and critical-timing-path information from a memory layout and automatically build a parametric model that can be used with Spice and other circuit simulators to verify the performance of the block. The company claims that MemChar cuts time-to-market for memory-based ICs (including those with SRAM, ROM and other specialty memories).

Accelerated technology movement and frequent Spice model changes are among the driving forces for a memory characterization tool, Wei said. For 0.15 micron and below, a single process may have several versions: one for high density, another for high speed and a third for low power, for example. Without automation, characterization can prove a huge task.

The gap is increasing between modern technology and conventional characterization. Typically, characterization requires segmenting and parameterizing a design, said Wei. Spice analog-circuit simulation is preferred for accuracy, since its models and equations often account for nonlinear effects. IP characterization models based on data extracted from layout can be used to automatically build critical-path netlists and to optimize circuits.

MemChar represents a "black-box" model generator with four modules: a simulation stimulus generator, a critical-path circuit builder called SpiceCut, a circuit simulation manager and a timing database generator. MemChar taps data sheet specifications to automatically generate the simulation stimulus and controls, such as set-up/hold time and minimum clock width.

To speed runtime for hundreds of simulations, the SpiceCut module builds a critical-path netlist for circuit and RC reduction. The circuit simulation manager is then called for running simulations automatically in "sweep" or "optimization" loops with the generated Spice netlists. Next, the timing data obtained from simulation results is organized as the timing database for models. The MemChar program automates all processes in the flow, including simulations and optimizations, said Wei.

MemChar is commercially available on Sun Solaris and Hewlett-Packard PA platforms. A floating license for MemChar costs $100,000 with optimization modules included.

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