RF ICs, embedded memories to get
airing at DAC
By Stephan Ohr
May 30, 2002
(1:21 p.m. EST)
FRANCISCO — RF IC design platforms will be among the tools
clamoring for attention when the 39th annual Design Automation
Conference (DAC) opens June 10 in New Orleans. RF design tool
startup Xpedion Design Systems Inc. will add fuel to the war
of words already being waged by Agilent Technologies and
Ansoft Corp., as the two latter companies unveil competitive
offerings at the show.
Elsewhere at DAC, fast-circuit-simulator manufacturers Nassda Corp. and Legend Design Technology
Inc. will demonstrate the approach's application to
embedded memory characterization, and a panel will explore the
technology issues attached to the development and sale of
analog intellectual property.
The brouhaha in RF IC design tools began in February, when
Agilent Technologies' EEsof group announced
"far-reaching" partnership with Cadence Design Systems Inc.
Agilent is arguably the "2,000-pound gorilla" among RF design
tool vendors and is the fifth-largest EDA software supplier,
said marketing market Jim Tabuchi. Cadence, meanwhile, is
inarguably the largest supplier of IC design tools: Its Analog
Artist platform has an installed base of more than 15,000
The partnership, which covers joint research and
development, is intended to create a single RF IC design flow
on the Cadence platform.
But no sooner was the partnership announced than RF design
tool competitors began positioning themselves against it.
Former Cadence marketer James Spoto, now president of Applied
Wave Research Inc., called Agilent tools slow and
inefficient compared with AWR's, and AWR sought its own
position on the Cadence IC design platform, via Cadence's
More recently, Ansoft
Corp. declared its intention to compete with Agilent in
the RF IC design sector with the introduction of Ansoft
Designer. Although it had formerly partnered with Agilent on
high-frequency structure simulators, Ansoft's design
translators and links to the Cadence design environment
position Ansoft Designer as more of a head-on competitor to
Agilent's Advanced Design System (ADS).
Ansoft Designer includes a "solver-on-demand" technology
that lets users move easily among physics-based
electromagnetic models, circuit models, system-level
behavioral models and others. (Access to RF and GaAs foundry
models has been a coveted Agilent strength.) Ansoft is
identified as a Platinum Partner in Cadence's Connections
program, which means its tools can be invoked from the Cadence
The latest challenge comes from startup Xpedion Design Systems,
which claims that version 3.1 of its Golden Gate simulation
tool, to be shown at DAC, will run circles around Agilent's
offering on computationally intensive RF analysis and
visualization tasks, such as adjacent channel power ratio and
third-order intercept. Roger Bitter, Xpedion's chief
technology officer, claims that his tools even deliver faster
results than Agilent's on harmonic balance simulation,
traditionally an EEsof forte.
For its part, the Agilent-Cadence team has been adamant
that the partnership came at the behest of its customers —
large players in RF IC design, like Philips Semiconductors,
STMicroelectronics and Infineon, that use both Agilent and
Cadence Design tools for RF IC development. Such customers had
been insisting that the tools be made to work together, said
Agilent EEsof marketing manager Charles Plott and Cadence RF
platform marketing director Les Spruiell.
Agilent's and Cadence's demonstration at DAC will reveal
the first results of their joint R&D program. Currently,
Cadence's Analog Artist and Agilent's ADS invoke separate
simulation and layout flows on the road to final layout and
verification. The program looks to create a single design flow
for RF ICs.
In the first phase, Agilent EEsof's display and analysis
tools will be brought completely into the Cadence environment.
In operation of the platform tools, the user could call forth
Cadence Spectre RF (for time-domain representations) and
Agilent EEsof's harmonic balance simulator (for
frequency-domain simulation) and other Agilent tools from the
same Cadence interface. Results of the simulations would be
displayed in a Cadence screen window with Agilent's plotters.
The second-phase incarnations of the tools will incorporate
intelligence into the selection of the simulation tool in the
RF IC design environment. Instead of selecting a Spice-like
circuit simulation or a harmonic-balance simulation, the user
would indicate the kind of data desired, and the tools would
automatically select and run the appropriate simulator or
simulators, said Joe Civello, Agilent's ADS platform manager.
Some DAC activity will attest to the growing concern that
digital CMOS IC designers — even memory designers — have about
analog effects. Nassda (Santa Clara, Calif.) will demonstrate
an embedded memory analysis tool, as will Legend Design
Technology (Sunnyvale, Calif.).
While Nassda has always specialized in circuit simulation
for large ICs, its Lexsim product is the first EDA tool to
model IR drops in nanometer ASICs, claimed product marketing
manager Simon Young. IR drops are the voltages dissipated by
the interconnect structures that reside between the supply
rail and the actual CMOS circuit.
IR drop is always a problem, but it is especially acute in
nanometer circuits (130 nm and below), where IR drops consume
a higher proportion of a lower supply voltage, Young said.
Thus, an extraordinarily fast tool is required to support
post-layout full-chip simulation of embedded memory at the
circuit level, he said.
Nanometer memories are particularly troublesome to
characterize, agreed You-Pang Wei, marketing manager at Legend
Design Technology, which will release a post-layout memory
verification tool dubbed MSim at DAC. Legend, known for
expertise in fast circuit simulation, typically uses a
parameter matrix (rather than a continuum) to simplify the
computational burdens and speed the process.
But simulation accuracy limits the reduction that can be
applied to nanometer structures. With 0.18-micron technology,
the simulation could be simplified as a 3 x 3 matrix,
simulating "typical," "low" and "fast" memory access values,
Wei said. With 0.13-micron technology, the matrix is more like
7 x 7.
But for 100-nm technology, a 10 x 10 matrix is required to
account for all the variations in memory performance.
Simulation performance is maintained by parallel processing on
multiple Linux machines, Wei said.
Analog IP hurdles
As if the DAC product introductions will not provide enough
analog concerns, designers can also attend a Tuesday (June 11)
afternoon panel devoted to the technology obstacles plaguing
the analog intellectual property (IP) business. Because the
performance of analog circuits is so bound to the behaviors of
devices in specific processes, many believe that the trade of
analog IP for use on larger system-on-chip devices can never
be made without an entire engineering team's accompanying the
The panel will feature assessments from tool vendor
Cadence, foundry Taiwan
Semiconductor Manufacturing Co., intellectual property
marketers Antrim Design
Systems Inc. and Nurlogic Design Inc. and
their large-company customers Hitachi Ltd. and Infineon Technologies