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EE Times: Design News
Legend Design upgrades memory characterization tool
(06/03/2005 12:57 AM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=164300014
 
SAN FRANCISCO — Legend Design Technology Inc. has upgraded its CharFlo-Memory characterization tool, adding new capabilities for improving silicon yields, the company said Thursday (June 2).

The upgrades addresses the modeling optimization and reliability checks against signal integrity and noise-margin for embedded memories on system-on-chip (SoC) designs, the company said.

According to Legend Design, the new release of CharFlo-Memory can ensure high yields of memory intellectual property (IP), which occupies the majority of SoC silicon. The company said the yield improvements have been achieved by:

  • Using the exact instance characterization for various process, voltages and temperatures rather than just roughly interpolated or extrapolated from table models.
  • Performing reliability checks at circuit-level after recognizing the structures and patterns of memory designs.
  • Enabling the layout parasitic RC extraction by providing only critical nets to be extracted.

    Legend Design (Santa Clara, Calif.) said CharFlo-Memory has been adopted by major foundries, IDMs and fabless design companies such as Taiwan Semiconductor Manufacturing Co. Ltd (TSMC), United Microelectronics Corp. (UMC), Broadcom Corp., Marvell Technology and most Japanese semiconductor companies. The timing and power models generated have been proven in SoC designs, including 65 and 90 nanometer technology, the company said.

    CharFlo-Memory tool is available now, starting at $250,000 for a perpetual license.

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