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Posted: 10:00 a.m., EDT, 6/8/98

IP development tools aide characterization of embedded memories

By Stephan Ohr

LOS ALTOS, Calif. Legend Design Technology Inc. has expanded its line of analog simulators to perform intellectual-property (IP) characterization for embedded-memory designs. GDS-Cut and IP-Char, which will be shown at booth 752 at the Design Automation Conference, allow rapid characterization of various large circuit blocks, including embedded memories.

The tools follow last year's introductions of Spice-Cut, which trims circuit-simulation time, and RC-Cut, an RC-reduction tool based on Carnegie-Mellon's Asymptotic Waveform Emulation (AWE). The simulators can be integrated or used independently.

GDS-Cut is a layout-reduction tool that trims layout extraction time. IP-Char is an IP-characterization tool for creating timing models in a .lib file format. Together, they can reduce the time it takes to perform analog-circuit characterization of a dense logic block with a large number of transistors.

IP-Char is designed for four types of circuits, said Che-Cheng Lin, technology officer at Legend Design Technology: embedded memories, combinatorial designs, sequential designs and I/O cells.

To create a timing model (such as Synopsys' .lib file), IP-Char generates a stimulus and analyzes the results. A looping setup is often required to ensure complete results. The simulation engines can be any Spice (or Spice-like) simulator, such as HSpice. But to make the characterization task feasible for large designs, circuit reduction is required.

In operation, the layout reduction tool, GDS-Cut, removes redundant parts of a layout, which are typically not needed in simulation. The layout reduction is most efficient for regular structures, such as memory arrays.

After layout extraction, the size of an extracted circuit may still far exceed the limit of a circuit simulator, Lin pointed out. Circuit-level reduction locates the most critical parts of the circuit and identifies their loading. If a large number of resistors exist in the net-list, Lin said, RC reduction can be used to trim the circuit size.

The design flow is claimed to reduce large designs by as much as 99 percent, but with Spice-level accuracy. According to Legend Design, one customer used GDS-Cut on a 4-k x 4 SRAM and reduced the layout from a full array with 105,039 MOSFETs to a ring with 38,823 MOSFETs. SpiceCut then reduced the net-list to 2,038 MOSFETs for critical-path simulation. The circuit was simulated in less than 5 minutes using HSpice, with claimed accuracy within 1 percent.

GDS-Cut takes GDS II files as its input and performs automatic memory-array recognition via proprietary algorithms. The geometry for a large-chip layout is reduced using such techniques as a quad list and quad tree. The reduction is typically a ring, said Lin, but the hierarchy of the original cells is retained as much as possible. The output of GDS-Cut is a reduced layout in GDS II format.

IP-Char is an IP (megacell) characterization program that includes a stimulus-generation module, looping process and controls, a Spice-results analysis and a library (.lib) generator module. It also analyzes timing and power. It is useful for standard-cell characterization and can handle multiple states in IP logic functions.

The tools will ship in the third quarter. They run under Unix on Sparc and HP workstations.


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