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Suppliers nudge analog EDA forward
By Stephan Ohr
EE Times
(06/09/00, 7:40 p.m.
EST)
Analog synthesis is an interesting step closer with the Neo Circuit
tool privately demonstrated here by Neo Linear. This is the "front-end" to
a complete synthesis system that Neo Linear hopes to formally announce
before the end of this year.
In operation of the tool, the user inputs an unsized schematic and a
list of performance criteria the circuit is supposed to meet. The system
uses the designer's own verification environment to try out alternatives,
and to generate a sized schematic. Neo Linear's existing Neo Cell tool
completes the process by converting the sized schematic to a buildable
cell layout. A user's test bench serves as an additional input at this
stage.
An important feature of the tool set is that it fits into the design
environment of the user, and harnesses the user's own verification
process. The tool is useful for four primary tasks, said Anthony Gadient,
vice president of engineering at Neo Linear. They are: designing a new
circuit; exploring circuit alternatives; migrating an existing circuit to
a new process; or totally retargeting an existing circuit.
The biggest difficulty is entering an entire circuit with all its
constraint information into the system, said Gadient. Even for a small
circuit with 39 elements, the entering of constraint information took an
entire day. Generating a sized circuit net-list, optimizing and generating
a cell layout will take considerably less human effort, though almost as
much run-time.
Neo Linear's Pittsburgh neighbor, Ansoft, was quietly demonstrating a
model technology called "Full Wave Spice" at DAC. This technology embeds
frequency-sensitive behavior into Spice models for various devices and
interconnects. This allows high-frequency responses to be examined, swept
and plotted in the time domain with conventional simulators like PSpice,
HSpice, or Ansoft's own MaxwellSpice, said Zoltan Cendes, Ansoft's
chairman and chief technology officer.
Ansoft's tools have always excelled at using Maxwell's equations to
depict 3-D radiation patterns. Though microwave engineers will utilize S
parameters to depict RF circuit behavior, engineers grounded in
lower-frequency circuit depictions would want to see these radiations
depicted as voltage and currents about a node, Cendes said.
Full Wave Spice effects what Cendes called a "mode to nodes"
conversion, and the frequency response is depicted as a "voltage
occurrence" about a node or terminal point. "Frequency-dependent behavior
is very complex," Cendes said. Full Wave Spice embeds much of the
"unevenness" of frequency response into a device model, where it can be
plotted on an amplitude chart. Applications for the technology will
include the analysis of OC-48 (2.4-Gbit/second) Sonet circuits, as well as
the new-generation OC-192 (10-Gbit/s) circuits. The Full Wave Spice
modeling capability will be embedded into the new version 8.0 release of
the high-frequency surface simulator (HFSS).
The increasing use of embedded memories in IC designs has prompted new
models for timing and power analysis. Legend Design's MemChar provides
automatic memory IP characterization for system-on-chip designs.
Spice-based, it claims an accuracy that other tools have difficulty
matching.
Memory characterization Legend's ability to characterize different types of memory — up to 100
different configuration blocks of SRAM, ROM and other specialty memories
with 20 to 30 timing parameters — stems from its circuit reduction
techniques, said You-Pang Wei, Legend's marketing director. While most of
these are set-up time, hold time, and minimum pulse width descriptions,
there will be a huge number of iterations to describe the circuit.
An accurate timing and power model is a prerequisite for full-chip
simulations, verifications and synthesis, said Wei. To generate timing and
power models, the characterization will need a large number of circuit
simulations with the up-to-date Spice models.
Circuit reduction effectively builds "critical-path" information for
the circuits being simulated. Legend's previously introduced SpiceCut tool
has been successfully used for circuit reduction in a large number of
designs. It uses AWE (Carnegie Mellon's asymptotic waveform extraction) RC
reduction module.
AWE takes into account critical coupling effects and looks for the
optimized set-up time, hold time and minimum pulse width. From this,
SpiceCut can automatically generate the stimulus and controls of
bi-section models used for optimization.
Analog IP For its part, Nurlogic Design concentrates on analog intellectual
property (IP). The company's I/O compiler — a Web-based tool that helps
designers select to drive strengths, loads and fan out capability for ASIC
output pads — was introduced at DAC. The tool allows users to specify
several different drive levels, including TTL and CMOS for selected output
pads.
A ground plane with power bus and isolation techniques for analog and
digital circuit segments are among the IP available from Nurlogic.
Customers include several communications IC makers, like Broadtree,
Vitesse, AMCC, Level One, 3Dlabs and DSP Group.
The PLLs and data converter IP that Nurlogic markets is targeted at
digital designers who are looking to move blocks around. But the company's
PromenADE analog IP introduced at DAC are targeted more toward the
analog-savvy designer, said Lisa Lipscomb, vice president of marketing.
The new IP offerings include analog design elements such as MOSFETs,
diodes, resistors and metal capacitors.
The company used IBM's 7FS 0.18-micron process models, and Cadence's
Analog Artist to capture symbols and parameterized models. "We want
designers to be able to vary the metal width with the current density,"
she said.
Nurlogic president Dave Matty said, "This is the stuff that makes a
great analog designer even better."
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