Home : Design  |
Circuit reduction speeds timing verification
By Stephan Ohr
EE Times
(06/09/99, 5:22 p.m.
EST)
SpiceCut-MP is a circuit-reduction tool that creates critical-path
simulation net-lists for bus, clock and multiple paths with complete
couplings. SpiceCut-DRAM generates a critical-path net-list for DRAM
circuit simulation. These tools build on Legend's SpiceCut-Memory
circuit-reduction technology. SpiceCut technology complements existing
circuit simulators, static timing analyzers and layout-extraction tools
for post-layout verification, said Che-Cheng Lin, project manager at Legend Design (Sunnyvale, Calif.).
Ordinarily, verifying timing data generated by static timing-analysis
tool can be tedious. Designers need to assure all loadings, related paths
and parasitics are included during the construction of the critical path.
Furthermore, all inputs of logic elements need to be sensitized to ensure
the net-list is ready for simulation. These contingencies cannot be put
into Spice without a great deal of trial and error, said Lin.
SpiceCut-MP effectively automates the generation of critical-path
circuits based on layout-extracted net-lists such as DSPF. The coupling
effects are fully modeled — not just delay information from static timing
analysis. Capacitance coupling, which usually has an impact on the
performance buses, can now be completely simulated with Spice, according
to Legend.
Bus-contention analysis In addition, SpiceCut-MP can extract the circuit needed for
bus-contention analysis by modeling it as multiple paths with user's input
specification. An integrated circuit net-list including latches, clock
tree, buses and interconnect RC networks is then generated from
layout-extracted circuit data in DSPF. In addition, the necessary
sensitization on nodal state by SpiceCut-MP is automatically assigned to
complete the Spice net-list generation.
SpiceCut-MP can also enhance the post-layout timing-verification flows
based on the library timing and SDF delay (like Cadence's Pearl or
Synopsys' PrimeTime). Instead of the conventional method of creating the
critical-path net-list from DSPF by hand and sensitizing the circuits
manually, SpiceCut-MP can automatically extract the Spice net-list of a
given path or multiple paths with properly sensitized logic states.
SpiceCut-DRAM, an expanded version of Legend's SpiceCut-Memory SRAM and
ROM analyzer, offers memory designers the capability to automate DRAM
circuit generation for Spice simulation. Because DRAM designs are highly
process dependent, an automated critical-path generation methodology will
support Spice simulation, said Lin.
SpiceCut-DRAM, based on newly developed algorithms, looks for the
regularities of critical circuit elements — such as sense amplifiers. This
auto-sensing capability automates the identification of active word lines
and active bit lines to generate the equivalent circuit of a memory array
accurately. Its dynamic-loading feature examines loading on
voltage-dependent elements to reduce transistor count and also maintain
accuracy. SpiceCut-DRAM also organizes all necessary subcircuits, controls
and initializations in the reduced Spice net-list for easy loading into a
simulator.
Pricing for SpiceCut-MP starts at $50,000. The price of SpiceCut-DRAM
with supporting software and setup services is listed at $160,000.
 |
|
|
| ||||
 |
| All material on this site Copyright © 2001 CMP Media LLC. All rights reserved. |
| |
|
|
