EE Times: Design News
Tool promises characterization of yield models for memory IP

SAN FRANCISCO — Legend Design Technology Inc.'s CharFlo-Memory toolset has been extended for characterization of design-for-manufacturability (DFM) parametric yield models of memory intellectual property (IP) in system-on-chip (SoC) designs, the company said.

CharFlo-Memory has been successfully adopted by major foundries, IDMs and fabless design companies for automatic memory IP verification and characterization, Legend (Santa Clara, Calif.) said.

According to Legend Design, most DFM companies working on parametric yield models deal with only cells or gates, not memory IPs. But memory IPs have taken the majority of chip area in most SoC designs.

With patented technologies, Legend's CharFlo-Memory enables the parametric yield models of memory IPs, according to the company. The tool can automatically generate critical-path circuits and critical-yield signals, Legend Design said.

CharFlo-Memory is available now, starting at $120,000 for an annual time-based license, Legend Design said.