EE Times: Design News Jazz Semi adopts Legend's tools for SoC design

(10/05/2005 12:21 PM EDT) URL: http://www.eetimes.com/showArticle.jhtml?articleID=171203235

MANHASSET, N.Y. — Legend Design Technology Inc., a supplier of IP characterization and circuit simulation software, announced that wafer foundry Jazz Semiconductor has adopted its CharFlo-Memory and MSIM tools to recharacterize on-chip memory instance models at various process, voltage and temperature (PVT) corners. "For low-power designs, our customers need to lower power consumption, which can be achieved by minimizing the voltage supply, which is different from the voltage in corner models provided by memory compiler vendors," said Rajiv Gupta, director of IP and design services at Jazz Semiconductor (Newport Beach, Calif.), in a statement. "Therefore, timing and power models of memory instances must be re-characterized to prevent design failures and low yields. On-chip noise is a limiting factor for lowering the voltage supply in low-power designs. CharFlo-Memory from Legend (Santa Clara, Calif.) helps to optimize voltage supply by analyzing the signal versus noise margin at all possible voltage levels. By providing critical nets to extract, Char-Flo Memory enables layout parasitic extraction on critical-path circuits only. This helps speed layout parasitic extraction.

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