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The Need
Building 'critical-path' circuits to reduce simulation time has become very necessary,
especially for characterization at multiple slew rates, multiple loadings and multiple PVTs.
To characterize setup and hold time, only a small critical-path circuit is needed with
measurement nodes for simulation, and full circuit may not help.
The Characterization Flow
The Functions
Verify and Debug Circuit
- Verifies memory structure from layout-extracted netlist.
- Checks the decoder function by toggling all address patterns, and simulating them.
- Locates worst and best word line by running Spice simulation on each pattern automatically and,
- ERC analysis over entire chip
Build 'Critical-Path' Netlists
- Creates a small equivalent circuit for SPICE simulation (e.g. access time) by removing the redundancy and remodeling memory arrays
- Builds bi-section models for setup / hold time and minimum clock width
- Performs AWE RC reduction
- Provides circuit reduction for power analysis
The Applications
- Post-layout verification and simulation of high performance memory designs
- Characterization and simulation of memory for generating timing and power models
- QA and debugging
Locate Critical-Path of Memory Design
SpiceCut-MemoryTM can exhaustively simulate all address patterns, automatically verify
the corresponding wordline, and obtain the timing from address change to wordline's.
Reliability Checking with Simulators
SpiceCut-MemoryTM can build 'critical-path' circuits, which can be simulated by various
commercial and in-house simulators.
The reliability can be checked by the sensitivity of simulators.
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