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Turbo-MSIM is a high-speed and high-capacity circuit simulator with SPICE-like accuracy.Turbo-MSIM is ideal for full-chip circuit simulations.
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  • Accelerated simulation speed
    Simulation speed is orders of magnitude faster than conventional Spice simulators.
  • Full-chip simulation capacity
    Efficiently simulates full-chip designs, either hierarchical or flattened netlists.
  • Exceptional accuracy
    Turbo-MSIM uses optimized time-based algorithms and proven models to deliver silicon-accurate results.
  • Scalable speed, capacity and accuracy
    Achieves best-in-class throughput with scalable speed capacity and accuracy.
  • Ultimate post-layout analysis
    Enables speedy post-layout simulation and includes state-of-the-art RC reduction.


  • Full-chip simulations for SoC designs
    Provides the capacity for full-chip simulation, either hierarchical circuit or flatterned layout-extracted netlist.
  • Functional verification
    Supports transistor-level functional verification, with vector input stimulus and vector output verification (VEC and VCD).
  • Timing and power analysis
    Performs transient analysis for timing verification and accurate power simulation, especially for leakage power. Turbo-MSIM is extraordinarily accurate for circuits with multiple voltage sources.
  • Memory and mixed-mode designs
    Proficiently recognizes repeated structures in memory circuits to optimize simulation throughput. Incorporates advanced algorithms and interfaces for mixed-mode designs.


  • Tabular device models for speed-up
    Generates tabular device models from complicated analytical models. Table-lookup models facilitate much faster simulation speed.
  • Latency detection for throughput
    Simulates only active circuits by latency detection to dramatically enhance speed.
  • Subcircuits and hierarchy rebuilding
    Extracts sub-circuits and re-build hierarchy from flatterned circuit for speed and memory efficiency.
  • Advanced RC reduction
    Built-in RC reduction modules are used to enhance the performance by reducing the size of circuit matrix during DC and transient iterations.
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