Legend - Success Story at TSMC
TSMC's High-Performance Memory Compiler Characterized by Legend Design Technology Toolsets
By Legend Design Technology and TSMC (Taiwan Semiconductor Manufacturing Company)
Santa Clara, California - July 10, 2003 - One of the challenging aspects of System-on-Chip (SoC) design
is integrating embedded memory. TSMC, the industry's leading foundry, recently
made an advance in this area with two newly developed memory compilers for its
0.13-micron Single-Port and Dual- Port SRAM compilers. To characterize, validate,
and verify the compiler-generated models, TSMC turned to Legend Design Technology's
unique layout-based memory characterization EDA toolsets.
"Designers will greatly appreciate the 0.13-micron Single-Port and Dual-Port
SRAM compilers for their reliability, accuracy, and simulation coverage,"
said Kuo Wu, TSMC's Deputy Director of Design and e-Services Marketing.
"With Legend's SpiceCut™ and MemChar™ toolsets, our memory models were
characterized in real-time on a per-instance basis to reflect the reality of
the silicon, rather than using the standard methods of interpolation or
extrapolation."
Meanwhile, TSMC's new 0.25-micron Single-Port SRAM compiler creates SRAM
macro with a 7.56 um2 bit cell, a significant improvement over the earlier
10.95 um2 bit-cell size is under development and will be released at Q4/2003.
This 0.25um SRAM compiler enables greater memory density and lower power consumption.
Accurate and efficient characterization can be attributed to Legend's toolset.
Legend Design Technology's SpiceCut™ and MemChar™ software tools automate the
time-consuming, error-prone processes associated with embedded memory characterization.
The toolsets can be used to build critical path circuits, configure simulations,
and generate timing/power models for system simulation. With SpiceCut, TSMC automated
optimal critical path circuits for both timing and power from 'Ring Shape' extracted
netlists. With MemChar, TSMC automatically generated all the stimuli, controls, and
measurement statements needed to run concurrent simulations.
"By incorporating Legend's 'Ring Shape' methodology to set up layout extractions
for large memory instances, TSMC improved parasitic RC extraction time for 4Mb SRAM
by an order of magnitude," said Fred Wang, TSMC's Senior Director of Design Services.
"MemChar's patented 'Bisection Mode' simulation technique contributes to the robustness
of the TSMC/Legend generated models," said You-Pang Wei, President of Legend Design
Technology, Inc. "This exhaustive binary iterative search determines the optimum
setup and hold times, eliminating the damaging effects of glitches, racing conditions,
and unsettled states inside the memory circuits."
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